Field of the Invention
The present disclosure relates to the technical field of display, more particularly, relates to a shift register unit, a gate electrode drive circuit and a display apparatus.
Description of the Related Art
As a touch-sensitive display apparatus develops, the requirement for quality of it becomes more and more. In-cell touch technology is applied widely due to its advantages such as low thickness and high touch sensitivity.
An in-cell touch element is integrated into a display panel to impart the touch-sensitive function to the panel itself such that the touch-sensitive effects and applications can be achieved without being adhered and assembled to the touch-sensitive panel otherwise. A typical TFT-LCD (Thin Film Transistor-Liquid Crystal Display) may be taken as an example, which has the following advantages: the touch-sensitive element may be produced finally in a TFT-LCD standard process; as the touch-sensitive panel does not need to be arranged additionally, the problem of adhering and alignment is avoided, the weight and thickness are reduced significantly, and the product becomes lighter. Use of the embedding technology may eliminate the frame of the display apparatus product, so as to achieve full plane design, and thus the product design may become concise and the application field becomes wider.
The conventional in-cell touch technology typically uses projection multiple point capacitance touch. Collection of its touch sensitive signals is achieved by signal lines located in two layers. The signal lines in one layer are drive lines (Tx lines) and the signal lines in the other layer are sensitive lines (Rx lines). The wiring direction in any one of the two layers is perpendicular to that in the other layer. In practice, all of drive lines are driven alternatively by means of scans and it measures whether there is a capacitance couple effect in a certain point on the sensitive lines crossed with the respective drive lines. By scanning one by one, an exact touch point position may be obtained and multiple point touch may be achieved.
For the conventional touch-sensitive display apparatus, the pixels and scan lines on the same column or row will be interfered with each other when they are charged simultaneously. Thus, the processes of the pixel charging and of the scan are typically performed separately in time, in particular, generally in two timing modes of V-Blank and H-Blank in one frame. V-Blank mode means within one frame a period is left for touch-sensitive signal scan after all of pixels have been charged, that is, the pixel charging operation and the touch-sensitive scan are performed separately. This mode can only support the same refresh rate of touch scan as the refresh rate of the display screen (in a ratio of 1:1). If the refresh rate of the display screen is 60 Hz, that of the touch scan can only be 60 Hz. In order to improve the touch sensitivity, it is crucial to enhance the frequency of touch scan. A touch refresh rate of 120 Hz or more is necessary if it is desired to achieve the touch experiences of high performance.
H-Blank mode may improve the refresh rate for touch scan efficiently. This mode remains a period for performing a part of touch signal scan in a charging interval of a certain rows of pixels in one frame, that is, the pixel charging operation and the touch scan are performed alternatively. This mode can support a touch scan refresh rate greater than the display screen refresh rate, that is, it may be multiple of the display screen refresh rate. The in-cell touch scan timing for achieving double of display refresh rate by H-Blank mode may be illustrated in FIG. 1. By dividing the display scan operation into two sections equally, after each of the sections ends up, the pixel scan GOA (Gate Drive on Array) circuit is stopped temporarily working, one scan (Tx scan) is performed for all of touch-sensitive lines. Thus, in one display scan, two touch scans may be done to achieve a touch scan having the refresh rate double of the display screen refresh rate.
The conventional GOA circuit typically includes a plurality of cascaded shift register units. They may have structures as illustrated in FIG. 2. These shift register units are connected to those in adjacent line respectively one by one. Each of the shift register units corresponds to one row of gate lines. Each row of shift register units may pre-charge the next row of the shift register units while each row of shift register units outputs the gate drive signals, in order to ensure the next row of shift register units to achieve the output in the next clock period. In the prior art, as illustrated in FIG. 3, 4T1C is taken as an example of the shift register unit having the simplest structure. When the H-Blank timing scan is performed as illustrated in FIG. 1, as the (N/2+1)th row of shift register units is the earliest row for the second ½ display scan, but its pull up control node PU has been charged into a high level when outputs are done at the (N/2)th. As there is a rather long scan period between the (N/2)th row output and the (N/2+1)th row output, the potential at the node PU may be leaked by the connected TFT so as to seriously degrade the pre-charging of the (N/2+1)th row of shift register units and thus the voltage will be reduced when the (N/2+1)th row of shift register units output. In this way, the row of pixels have insufficient charging rate and thus dark lines or bad bright lines may occur.